This thesis provides a thorough noise analysis for conventional CIS readout chains, while also presenting and discussing a variety of noise reduction techniques that allow the read noise in standard processes to be optimized. Two physical implementations featuring sub-0.5-electron RMS are subsequently presented to verify the proposed noise reduction techniques and provide a full characterization of a VGA imager. Based on the verified noise calculation, the impact of the technology downscaling on the input-referred noise is also studied. Further, the thesis covers THz CMOS image sensors and presents an original design that achieves ultra-low-noise performance. Last but not least, it provides a comprehensive review of CMOS image sensors.
Ultra Low Noise CMOS Image Sensors: Assim Boukhayma
Large Format CMOS Image Sensors:Performance and Design Suat Utku Ay
Ultra Low Noise CMOS Image Sensors:Springer Theses. 1st ed. 2018 Assim Boukhayma
A Biologically Inspired CMOS Image Sensor:Studies in Computational Intelligence. Auflage 2013 Mukul Sarkar, Albert Theuwissen
A Biologically Inspired CMOS Image Sensor: Mukul Sarkar, Albert Theuwissen
Erscheinungsdatum: 28.01.2017Medium: BuchEinband: GebundenTitel: Low-Power Cmos Digital Pixel Imagers for High-Speed Uncooled PbSe IR ApplicationsAutor: Margarit, Josep MariaVerlag: Springer-Verlag GmbH // Springer International Publishing AGSprache
This book describes the development of a new low-cost medium wavelength IR (MWIR) monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapor phase deposition (VPD) PbSe-based MWIR detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. In order to fulfill the operational requirements of VPD PbSe, this work proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation.